1. Field of the Invention
The invention relates to instruction decoding apparatuses, particularly those employed in microprocessors.
2. Prior Art
Microprocessors, as well as other computers, must often employ a decoder which decodes macro level instructions. In effect, the instruction is interpreted by the decoder and the decoder determines what must be done in the processor to execute the instruction. In many cases the microprocessor includes a memory for storing micro level instructions (microcode) and the decoder provides a look-up to the microcode.
In some microprocessors, macro level instructions are of fixed length (e.g., 32 bits) while in others, instructions can be of different lengths. It is a much easier task to decode instructions of fixed length, since for instance, the decoder knows where to find certain fields in the instruction. In contrast, with variable length instructions, an immediate data field, for example, may or may not be present and its starting point in the instruction will vary.
The Intel 386 microprocessor (Intel and 386 are trademarks of Intel Corporation) is an example of a microprocessor with variable length instructions. An instruction can be one byte wide, such as some MOVE instructions. Instructions can be up to 8 bytes wide (with no prefix). Moreover, with an instruction prefix or override, the length of the instruction can be substantially longer (e.g., 15 bytes). A single decoder to decode these variable length instructions in a single pass would be relatively complex, and perhaps more importantly, would consume a relatively large substrate area.
In the Intel 386 the variable length instructions are decoded over the course of several computer cycles. First the instruction prefix is examined followed by other fields. Execution of the instructions begins after complete decoding. With many instructions, the Intel 386 requires several cycles for decoding; for example, LOAD requires four cycles for the instruction to be decoded, STORE requires two cycles; JUMP, three cycles to 4.25 cycles. On the average approximately three cycles are required before an instruction is fully decoded. As will be seen with the present invention, these times are greatly reduced because of pipelining and the manner in which the instruction is decoded. Decoding time drops to an average of approximately 1.8 cycles.
The present invention is intended to be used in a microprocessor which is an improved version of the Intel 386 microprocessor. The Intel 386 microprocessor is described in numerous printed publications. The programming for this microprocessor is described in Programming the 80386, by Crawford and Gelsinger, published by SYBEX, 1987.